先进封装-从2D，3D到4D封装

[{"attributes":{"color":"var(--weui-FG-2)"},"insert":"失效分析 赵工"},{"insert":" "},{"attributes":{"color":"#576b95"},"insert":"半导体工程师"},{"insert":" "},{"attributes":{"color":"var(--weui-FG-2)"},"insert":"2023-02-04 03:09"},{"insert":" "},{"attributes":{"color":"var(--weui-FG-2)"},"insert":"发表于北京"},{"insert":"\n\n"},{"attributes":{"color":"#000000"},"insert":"电子集成技术分为三个层次，"},{"attributes":{"color":"#ff4c00"},"insert":"芯片上的集成"},{"attributes":{"color":"#000000"},"insert":"，"},{"attributes":{"color":"#ff4c00"},"insert":"封装内的集成"},{"attributes":{"color":"#000000"},"insert":"，"},{"attributes":{"color":"#ff4c00"},"insert":"PCB板级集成"},{"attributes":{"color":"#000000"},"insert":"，其代表技术分别为SoC，SiP和PCB（也可以称为SoP或者SoB）"},{"attributes":{"align":"justify","header":1},"insert":"\n"},{"attributes":{"align":"justify"},"insert":"\n"},{"attributes":{"color":"#333333"},"insert":"芯片上的集成主要以2D为主，晶体管以平铺的形式集成于晶圆平面；同样，PCB上的集成也是以2D为主，电子元器件平铺安装在PCB表面，因此，二者都属于2D集成。而针对于封装内的集成，情况就要复杂的多。"},{"attributes":{"align":"justify"},"insert":"\n\n"},{"attributes":{"color":"#333333"},"insert":"电子集成技术分类的两个重要判据：1.物理结构，2.电气连接(电气互连)。"},{"attributes":{"align":"justify"},"insert":"\n\n"},{"attributes":{"color":"#000000"},"insert":"目前先进封装中按照主流可分为"},{"attributes":{"color":"#ff4c00"},"insert":"2D封装、2.5D封装、3D封装"},{"attributes":{"color":"#000000"},"insert":"三种类型。"},{"attributes":{"align":"justify"},"insert":"\n\n"},{"insert":{"image":"https://files.eteforum.com/202302/b2691db556fc6bde.png"}},{"attributes":{"align":"center"},"insert":"\n"},{"attributes":{"align":"justify"},"insert":"\n"},{"attributes":{"background":"#fffb00","color":"#ff4c00","bold":true},"insert":"1，2D封装"},{"attributes":{"align":"justify"},"insert":"\n\n"},{"attributes":{"color":"#000000"},"insert":"2D封装是指在基板的表面水平安装所有芯片和无源器件的集成方式。2D封装上包括FOWLP、FOPLP等技术。"},{"attributes":{"align":"justify"},"insert":"\n\n"},{"attributes":{"color":"#33353c","bold":true},"insert":"物理结构"},{"attributes":{"color":"#000000"},"insert":"："},{"attributes":{"color":"#33353c"},"insert":"所有芯片和无源器件均安装在基板平面"},{"attributes":{"color":"#000000"},"insert":"，"},{"attributes":{"color":"#33353c"},"insert":"芯片和无源器件和 XY 平面直接接触"},{"attributes":{"color":"#000000"},"insert":"，"},{"attributes":{"color":"#33353c"},"insert":"基板上的布线和过孔均位于 XY 平面下方"},{"attributes":{"color":"#000000"},"insert":"；"},{"attributes":{"color":"#33353c","bold":true},"insert":"电气连接"},{"attributes":{"color":"#000000"},"insert":"："},{"attributes":{"color":"#33353c"},"insert":"均需要通过基板"},{"attributes":{"color":"#000000"},"insert":"（"},{"attributes":{"color":"#33353c"},"insert":"除了极少数通过键合线直接连接的键合点"},{"attributes":{"color":"#000000"},"insert":"）"},{"attributes":{"align":"justify"},"insert":"\n\n"},{"attributes":{"color":"#ff4c00"},"insert":"台积电的InFO："},{"attributes":{"align":"justify"},"insert":"\n"},{"insert":{"image":"https://files.eteforum.com/202302/a304f6fb951a7653.png"}},{"attributes":{"align":"justify"},"insert":"\n\n"},{"attributes":{"color":"#000000"},"insert":"台积电在2017年开发的InFO技术。InFO技术与大多数封装厂的Fan-out类似，可以理解为多个芯片Fan-out工艺的集成，主要区别在于去掉了silicon interposer，使用一些RDL层进行串连（2016年推出的iPhone7中的A10处理器，采用台积电16nm FinFET工艺以及InFO技术）。"},{"attributes":{"align":"justify"},"insert":"\n\n"},{"attributes":{"color":"#ff4c00"},"insert":"日月光的eWLB："},{"attributes":{"color":"#000000"},"insert":"与台积的InFO类似，都属于Fan-out技术"},{"attributes":{"align":"justify"},"insert":"\n"},{"insert":{"image":"https://files.eteforum.com/202302/439e54fceeb275bd.png"}},{"attributes":{"align":"justify"},"insert":"\n\n"},{"attributes":{"color":"#33353c","bold":true},"insert":"另外，还有一种"},{"attributes":{"color":"#ff4c00","background":"#fffb00","bold":true},"insert":"2D+ 集成"},{"attributes":{"align":"justify"},"insert":"\n\n"},{"insert":"2D+集成是指的传统的通过键合线连接的芯片堆叠集成。也许会有人问，芯片堆叠不就是3D吗，为什么要定义为2D+集成呢？"},{"attributes":{"align":"justify"},"insert":"\n\n"},{"insert":"主要基于以下两点原因："},{"attributes":{"align":"justify"},"insert":"\n\n"},{"insert":"1）3D集成目前在很大程度上特指通过3D TSV的集成，为了避免概念混淆，我们定义这种传统的芯片堆叠为2D+集成；"},{"attributes":{"align":"justify"},"insert":"\n\n"},{"insert":"2）虽然物理结构上是3D的，但其电气互连上均需要通过基板，即先通过键合线键合到基板，然后在基板上进行电气互连。这一点和2D集成相同，比2D集成改进的是结构上的堆叠，能够节省封装的空间，因此称之为2D+集成。"},{"attributes":{"align":"justify"},"insert":"\n\n"},{"attributes":{"color":"#ff4c00"},"insert":"物理结构"},{"insert":"：所有芯片和无源器件均地位于XY平面上方，部分芯片不直接接触基板，基板上的布线和过孔均位于XY平面下方；"},{"attributes":{"align":"justify"},"insert":"\n\n"},{"attributes":{"color":"#ff4c00"},"insert":"电气连接"},{"insert":"：均需要通过基板（除了极少数通过键合线直接连接的键合点）"},{"attributes":{"align":"justify"},"insert":"\n"},{"insert":{"image":"https://files.eteforum.com/202302/de5e8e7d7b7d7a9d.png"}},{"attributes":{"align":"center"},"insert":"\n"},{"attributes":{"background":"#fffb00","color":"#ff4c00","bold":true},"insert":"2.5D封装："},{"attributes":{"align":"justify"},"insert":"\n"},{"insert":"2.5D封装通常是指既有2D的特点，又有部分3D的特点，其中的代表技术包括英特尔的EMIB、台积电的CoWoS、三星的I-Cube。"},{"attributes":{"align":"justify"},"insert":"\n"},{"insert":"物理结构：所有芯片和无源器件均XY平面上方，至少有部分芯片和无源器件安装在中介层上（Interposer），在XY平面的上方有中介层的布线和过孔，在XY平面的下方有基板的布线和过孔。"},{"attributes":{"align":"justify"},"insert":"\n"},{"insert":"电气连接：中介层（Interposer）可提供位于中介层上的芯片的电气连接。"},{"attributes":{"align":"justify"},"insert":"\n\n"},{"insert":"2.5D集成的关键在于中介层Interposer，一般会有几种情况，1）中介层是否采用硅转接板，2）中介层是否采用TSV，3）采用其他类型的材质的转接板；在硅转接板上，我们将穿越中介层的过孔称之为TSV，对于玻璃转接板，我们称之为TGV。"},{"attributes":{"align":"justify"},"insert":"\n\n"},{"attributes":{"color":"#000000"},"insert":"所谓的TSV 指的是："},{"attributes":{"align":"justify"},"insert":"\n\n"},{"insert":{"image":"https://files.eteforum.com/202302/133fbd8f45bf59fc.png"}},{"attributes":{"align":"center"},"insert":"\n"},{"attributes":{"align":"justify"},"insert":"\n"},{"attributes":{"color":"#333333"},"insert":"硅中介层有TSV的集成是最常见的一种2.5D集成技术，芯片通常通过MicroBump和中介层相连接，作为中介层的硅基板采用Bump和基板相连，硅基板表面通过RDL布线，TSV作为硅基板上下表面电气连接的通道，这种2.5D集成适合芯片规模比较大，引脚密度高的情况，芯片一般以FlipChip形式安装在硅基板上。"},{"attributes":{"align":"justify"},"insert":"\n\n"},{"attributes":{"color":"#ff4c00"},"insert":"有TSV的2.5D集成示意图："},{"attributes":{"align":"justify"},"insert":"\n\n"},{"insert":{"image":"https://files.eteforum.com/202302/d2454310887385f6.png"}},{"attributes":{"align":"justify"},"insert":"\n\n"},{"insert":"硅中介层无TSV的2.5D集成的结构一般如下图所示，有一颗面积较大的裸芯片直接安装在基板上，该芯片和基板的连接可以采用"},{"attributes":{"color":"#ff4c00"},"insert":"Bond Wire或者Flip Chip"},{"insert":"两种方式，大芯片上方由于面积较大，可以安装多个较小的裸芯片，但小芯片无法直接连接到基板，所以需要插入一块中介层（Interposer），在中介层上方安装多个裸芯片，中介层上有RDL布线，可将芯片的信号引出到中介层的边沿，然后通过Bond Wire连接到基板。这类中介层通常不需要TSV，只需要通过Interposer上表面的布线进行电气互连，Interposer采用Bond Wire和封装基板连接。"},{"attributes":{"align":"justify"},"insert":"\n\n"},{"attributes":{"color":"#ff4c00"},"insert":"无TSV的2.5D集成示意图："},{"attributes":{"align":"justify"},"insert":"\n"},{"insert":{"image":"https://files.eteforum.com/202302/52acd3b97474cc35.png"}},{"attributes":{"align":"justify"},"insert":"\n\n\n"},{"attributes":{"color":"#ff4c00"},"insert":"英特尔的EMIB："},{"attributes":{"align":"justify"},"insert":"\n"},{"insert":"概念与2.5D封装类似，但与传统2.5D封装的区别在于"},{"attributes":{"bold":true},"insert":"没有TSV"},{"insert":"。也正是这个原因，EMIB技术具有正常的封装良率、无需额外工艺和设计简单等优点。"},{"attributes":{"align":"justify"},"insert":"\n"},{"insert":{"image":"https://files.eteforum.com/202302/60569ff52a5defee.png"}},{"attributes":{"align":"justify"},"insert":"\n"},{"attributes":{"color":"#ff4c00"},"insert":"台积电的CoWoS技术"},{"attributes":{"align":"justify"},"insert":"\n\n"},{"attributes":{"color":"#000000"},"insert":"台积电的CoWoS技术也是一种2.5D封装技术。根据中介层的不同可以分为三类，一种是CoWoS_S使用Si衬底作为中介层，另一种是CoWoS_R使用RDL作为中介层，第三种是CoWoS_L使用小芯片（Chiplet）和RDL作为中介层。"},{"attributes":{"align":"justify"},"insert":"\n\n"},{"insert":{"image":"https://files.eteforum.com/202302/29d8c955669c4f4e.png"}},{"attributes":{"align":"justify"},"insert":"\n\n"},{"insert":"台积电InFO（2D）与CoWoS（2.5D）之间的区别在于，CoWoS针对高端市场，连线数量和封装尺寸都比较大；InFO针对性价比市场，封装尺寸较小，连线数量也比较少。"},{"attributes":{"align":"justify"},"insert":"\n\n"},{"insert":"第一代CoWoS主要用于大型FPGA。CoWoS-1的中介层芯片面积高达约800mm²，非常接近掩模版限制。第二代CoWoS通过掩模拼接显着增加了中介层尺寸。台积电最初符合1200mm²的要求，此后将中介层尺寸增加到1700mm²。这些大型封装称为CoWoS-XL2。"},{"attributes":{"align":"justify"},"insert":"\n\n"},{"insert":"最近，台积电公布的第五代CoWoS-S的晶体管数量将增加20倍，中介层面积也会提升3倍。第五代封装技术还将封装8个128G的HBM2e内存和2颗大型SoC内核。"},{"attributes":{"align":"justify"},"insert":"\n\n"},{"attributes":{"color":"#ff4c00"},"insert":"长电科技XDFOI技术："},{"attributes":{"align":"justify"},"insert":"\n\n"},{"insert":{"image":"https://files.eteforum.com/202302/eaa87a4f39c23aa6.png"}},{"attributes":{"align":"justify"},"insert":"\n\n"},{"attributes":{"color":"#000000"},"insert":"相较于2.5D TSV封装技术，具备更高性能、更高可靠性以及更低成本等特性。该解决方案在线宽或线距可达到2um的同时，可实现多层布线层，另外，采用了极窄节距凸块互联技术，封装尺寸大，可集成多颗芯片、高带宽内存和无源器件。"},{"attributes":{"align":"justify"},"insert":"\n\n"},{"attributes":{"color":"#ff4c00"},"insert":"三星的I-Cube"},{"attributes":{"align":"justify"},"insert":"\n\n"},{"insert":{"image":"https://files.eteforum.com/202302/bf6861f87d4cedcc.png"}},{"attributes":{"align":"justify"},"insert":"\n\n"},{"attributes":{"color":"#000000"},"insert":"三星的具有的先进封装包括I－Cube、X－Cube、R－Cube和H－Cube四种方案。其中，三星的I-Cube同样也属于2.5D封装。"},{"attributes":{"align":"justify"},"insert":"\n\n"},{"attributes":{"background":"#fffb00","color":"#ff4c00","bold":true},"insert":"3D封装："},{"attributes":{"align":"justify"},"insert":"\n"},{"insert":"3D封装和2.5D封装的主要区别在于：2.5D封装是在Interposer上进行布线和打孔，而3D封装是直接在芯片上打孔和布线，电气连接上下层芯片。3D集成目前在很大程度上特指通过3D TSV的集成。"},{"attributes":{"align":"justify"},"insert":"\n"},{"attributes":{"color":"#ff4c00"},"insert":"3D集成和2.5D集成的主要区别"},{"insert":"在于：2.5D集成是在中介层Interposer上进行布线和打孔，而3D集成是"},{"attributes":{"color":"#ff4c00"},"insert":"直接在芯片上打孔（TSV）和布线（RDL）"},{"insert":"，电气连接上下层芯片。"},{"attributes":{"align":"justify"},"insert":"\n\n"},{"attributes":{"color":"#ff4c00"},"insert":"物理结构"},{"insert":"：所有芯片和无源器件均位于XY平面上方，芯片堆叠在一起，在XY平面的上方有穿过芯片的TSV，在XY平面的下方有基板的布线和过孔。"},{"attributes":{"align":"justify"},"insert":"\n\n"},{"attributes":{"color":"#ff4c00"},"insert":"电气连接"},{"insert":"：通过TSV和RDL将芯片直接电气连接"},{"attributes":{"align":"justify"},"insert":"\n\n"},{"insert":"3D集成大多数应用在"},{"attributes":{"color":"#ff4c00"},"insert":"同类芯片堆叠"},{"insert":"中，多个相同的芯片垂直堆叠在一起，通过穿过芯片堆叠的TSV互连，如下图所示。同类芯片集成大多应用在存储器集成中，例如DRAM Stack，FLASH Stack等。"},{"attributes":{"align":"justify"},"insert":"\n\n"},{"attributes":{"color":"#333333"},"insert":"同类芯片的3D集成示意图："},{"attributes":{"align":"justify"},"insert":"\n"},{"insert":{"image":"https://files.eteforum.com/202302/a999d1844b41867d.png"}},{"attributes":{"align":"justify"},"insert":"\n\n\n"},{"insert":"不同类芯片的3D集成中，一般是将两种不同的芯片垂直堆叠，并通过TSV电气连接在一起，并和下方的基板互连，有时候需要在芯片表面制作RDL来连接上下层的TSV。"},{"attributes":{"align":"justify"},"insert":"\n"},{"insert":{"image":"https://files.eteforum.com/202302/927e35288874f195.png"}},{"attributes":{"align":"justify"},"insert":"\n\n\n"},{"attributes":{"color":"#ff4c00"},"insert":"台积电的SoIC技术："},{"attributes":{"align":"justify"},"insert":"\n"},{"insert":{"image":"https://files.eteforum.com/202302/50467c35ac5279c2.png"}},{"attributes":{"align":"justify"},"insert":"\n\n\n"},{"attributes":{"color":"#000000"},"insert":"台积电SoIC技术属于3D封装，是一种晶圆对晶圆(Wafer-on-wafer)的键合技术。SoIC技术是采用TSV技术，可以达到无凸起的键合结构，把很多不同性质的临近芯片整合在一起，而且当中最关键、最神秘之处，就在于接合的材料，号称是价值高达十亿美元的机密材料。"},{"attributes":{"align":"justify"},"insert":"\n\n"},{"insert":{"image":"https://files.eteforum.com/202302/6c7d41c7470769ad.png"}},{"attributes":{"align":"justify"},"insert":"\n\n"},{"attributes":{"color":"#000000"},"insert":"SoIC技术将同质和异质小芯片集成到单个类似SoC的芯片中，具有更小尺寸和更薄的外形，可以整体集成到先进的WLSI（又名CoWoS和InFO）中。从外观上看，新集成的芯片就像一个通用的SoC芯片，但嵌入了所需的异构集成功能。"},{"attributes":{"align":"justify"},"insert":"\n\n"},{"attributes":{"color":"#ff4c00"},"insert":"英特尔的Foveros技术"},{"insert":"："},{"attributes":{"align":"justify"},"insert":"\n"},{"insert":{"image":"https://files.eteforum.com/202302/fc9097b93cfe9e4d.png"}},{"attributes":{"align":"justify"},"insert":"\n"},{"insert":"从3D Foveros的结构上看，最下边是封装基底，之上安放一个底层芯片，起到主动中介层的作用。在中介层里有大量的TSV 3D硅穿孔，负责联通上下的焊料凸起，让上层芯片和模块与系统其他部分通信。"},{"attributes":{"align":"justify"},"insert":"\n"},{"attributes":{"color":"#ff4c00"},"insert":"三星的X-Cube 3D封装技术："},{"attributes":{"align":"justify"},"insert":"\n"},{"insert":{"image":"https://files.eteforum.com/202302/a7ec71e45833ece6.png"}},{"attributes":{"align":"justify"},"insert":"\n"},{"insert":"使用TSV工艺，目前三星的X-Cube测试芯片已经能够做到将SRAM层堆叠在逻辑层之上，通过TSV进行互联，制程是他们自家的7nm EUV工艺。"},{"attributes":{"align":"justify"},"insert":"\n"},{"attributes":{"color":"#ff4c00"},"insert":"长电科技的扩展eWLB："},{"attributes":{"align":"justify"},"insert":"\n"},{"insert":{"image":"https://files.eteforum.com/202302/375fbd50cd8d4c90.png"}},{"attributes":{"align":"justify"},"insert":"\n"},{"insert":"长电科技基于eWLB的中介层可在成熟的低损耗封装结构中实现高密度互连，提供更高效的散热和更快的处理速度。3D eWLB互连（包括硅分割）是通过独特的面对面键合方式实现，无需成本更高的TSV互连，同时还能实现高带宽的3D集成。"},{"attributes":{"align":"justify"},"insert":"\n"},{"attributes":{"color":"#ff4c00"},"insert":"华天科技的3D-eSinC解决方案："},{"attributes":{"align":"justify"},"insert":"\n"},{"insert":{"image":"https://files.eteforum.com/202302/bfa5d763862edc18.png"}},{"attributes":{"align":"justify"},"insert":"\n"},{"insert":"华天科技称，2022年将开展2.5D Interpose FCBGA、FOFCBGA、3D FOSiP等先进封装技术，以及基于TCB工艺的3D Memory封装技术，Double Sidemolding射频封装技术、车载激光雷达及车规级12英寸晶圆级封装等技术和产品的研发。"},{"attributes":{"align":"justify"},"insert":"\n"},{"attributes":{"background":"#fffb00","color":"#ff4c00","bold":true},"insert":"4D 集成："},{"attributes":{"align":"justify"},"insert":"\n"},{"attributes":{"color":"#333333","bold":true},"insert":"物理结构"},{"attributes":{"color":"#333333"},"insert":"：多块基板以非平行方式安装，每块基板上都安装有元器件，元器件安装方式多样化。"},{"attributes":{"color":"#333333","bold":true},"insert":"电气连接"},{"attributes":{"color":"#333333"},"insert":"：基板之间通过柔性电路或者焊接连接，基板上芯片电气连接多样化。"},{"attributes":{"align":"justify"},"insert":"\n"},{"insert":"基于刚柔基板的4D集成示意图："},{"attributes":{"align":"justify"},"insert":"\n"},{"insert":{"image":"https://files.eteforum.com/202302/d4a15e9468af4d01.png"}},{"attributes":{"align":"justify"},"insert":"\n"},{"insert":"4D集成定义主要是关于多块基板的方位和相互连接方式，因此在4D集成也会包含有2D，2D+，2.5D，3D的集成方式"},{"attributes":{"align":"justify"},"insert":"\n\n"},{"insert":{"image":"https://files.eteforum.com/202302/d19af4342ea4e401.png"}},{"attributes":{"align":"justify"},"insert":"\n\n"},{"attributes":{"color":"#000000"},"insert":"来源：半导体封装工程师之家；作者：张竞扬"},{"attributes":{"align":"justify"},"insert":"\n"},{"insert":{"image":"https://files.eteforum.com/202302/5cdee3561fca3278.png"}},{"attributes":{"align":"center"},"insert":"\n"},{"insert":"sat无损样品内部分层检测icfalab"},{"attributes":{"align":"center"},"insert":"\n"},{"attributes":{"color":"var(--weui-FG-0)"},"insert":"半导体工程师"},{"attributes":{"align":"justify"},"insert":"\n"},{"insert":"半导体经验分享，半导体成果交流，半导体信息发布。半导体行业动态，半导体从业者职业规划，芯片工程师成长历程。"},{"attributes":{"align":"justify"},"insert":"\n"},{"insert":"71篇原创内容"},{"attributes":{"align":"justify"},"insert":"\n"},{"insert":"公众号"},{"attributes":{"align":"justify"},"insert":"\n\n"},{"insert":"\n"}]